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Abstract Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in the scalability of such platforms. Therefore, in this work, we propose an Ising machine platform that exploits the novel behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as classical Ising spins interacting through highly scalable and CMOS-process compatible ferroelectric-HfO 2 -based Ferroelectric FETs (FeFETs) which act as coupling elements. We experimentally demonstrate the prototype building blocks of this system, and evaluate the scaling behavior of the system using simulations. Our work not only provides a pathway to realizing CMOS-compatible designs but also to overcoming their scaling challenges. 

Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128 × 128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows ~22.6×/~14.1× increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes.

 

Abstract Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks. 

Lithium metal–selenium (Li–Se) batteries offer high volumetric energy but are limited in their cycling life and fast charge characteristics. Here a facile approach is demonstrated to synthesize hierarchically porous hollow carbon spheres that host Se (Se@HHCS) and allow for state-of-the-art electrochemical performance in a standard carbonate electrolyte (1 M LiPF 6 in 1 : 1 EC : DEC). The Se@HHCS electrodes display among the most favorable fast charge and cycling behavior reported. For example, they deliver specific capacities of 442 and 357 mA h g −1 after 1500 and 2000 cycles at 5C and 10C, respectively. At 2C, Se@HHCS delivers 558 mA h g −1 after 500 cycles, with cycling coulombic efficiency of 99.9%. Post-mortem microstructural analysis indicates that the structures remain intact during extended cycling. Per GITT analysis, Se@HHCS possesses significantly higher diffusion coefficients in both lithiation and delithiation processes as compared to the baseline. The superior performance of Se@HHCS is directly linked to its macroscopic and nanoscale pore structure: the hollow carbon sphere morphology as well as the remnant open nanoporosity accommodates the 69% volume expansion of the Li to Li 2 Se transformation, with the nanopores also providing a complementary fast ion diffusion path. 

This is the first report of molybdenum carbide‐based electrocatalyst for sulfur‐based sodium‐metal batteries. MoC/Mo₂C is in situ grown on nitrogen‐doped carbon nanotubes in parallel with formation of extensive nanoporosity. Sulfur impregnation (50 wt% S) results in unique triphasic architecture termed molybdenum carbide–porous carbon nanotubes host (MoC/Mo₂C@PCNT–S). Quasi‐solid‐state phase transformation to Na₂S is promoted in carbonate electrolyte, with in situ time‐resolved Raman, X‐ray photoelectron spectroscopy, and optical analyses demonstrating minimal soluble polysulfides. MoC/Mo₂C@PCNT–S cathodes deliver among the most promising rate performance characteristics in the literature, achieving 987 mAh g⁻¹at 1 A g⁻¹, 818 mAh g⁻¹at 3 A g⁻¹, and 621 mAh g⁻¹at 5 A g⁻¹. The cells deliver superior cycling stability, retaining 650 mAh g⁻¹after 1000 cycles at 1.5 A g⁻¹, corresponding to 0.028% capacity decay per cycle. High mass loading cathodes (64 wt% S, 12.7 mg cm⁻²) also show cycling stability. Density functional theory demonstrates that formation energy of Na₂S_x(1 ≤x ≤ 4) on surface of MoC/Mo₂C is significantly lowered compared to analogous redox in liquid. Strong binding of Na₂S_x(1 ≤x ≤ 4) on MoC/Mo₂C surfaces results from charge transfer between the sulfur and Mo sites on carbides’ surface.